jhauser-us
commented
1 week ago When it says the "value of mip.SEIP is simply the..." is it just saying the readable value or the actual value?
In the Privileged ISA's chapter titled "Control and Status Registers (CSRs)", in the section titled "Implicit Reads of CSRs", it says:
Unless otherwise specified, the value returned by an implicit read of a CSR is the same value that would have been returned by an explicit read of the CSR, ....
The "actual value" of mip.SEIP is no different from the readable value.
However, when mvien[9] = 0, mip.SEIP is unusual in having an underlying "software-writable bit" that contributes to its readable value. This strange arrangement is described in the Privileged ISA section titled "Machine Interrupt Registers (mip and mie)". See earlier AIA GitHub issue #64.
and of course mvip.SEIP is an alias of mip.SEIP when mvien.9 is 0.
That's not quite correct. When mvien[9] = 0, mvip.SEIP is an alias of the software-writable bit of mip.SEIP.
To answer your last question, at the end of your sequence, if the incoming supervisor-level external interrupt signal is still 0, then mip.SEIP should be 0. When mvien[9] = 0, mip.SEIP = (incoming SEI signal) || (software-writable bit SEIP). And because mvip.SEIP is an alias for the software-writable bit SEIP, it's equally correct to say that mip.SEIP = (incoming SEI signal) || mvip.SEIP.
The spec says
But when bit 9 of mvien is one, bit SEIP in mip is read-only and does not include the value of bit 9 of mvip. Rather, the value of mip.SEIP is simply the supervisor external interrupt signal from the hart’s external interrupt controller (APLIC or IMSIC).
When it says the "value of mip.SEIP is simply the..." is it just saying the readable value or the actual value?
The reason I ask is because the wording makes it seem like mip.SEIP doesn't actually "exist". The prior sentence says
In particular, for most purposes, the value of bit 9 of mvip is logically ORed into the readable value of mip.SEIP.
and of course mvip.SEIP is an alias of mip.SEIP when mvien.9 is 0.
Suppose mvien.9=0, and there was a write to mvip.SEIP=1 (which means mip.SEIP should also be 1). Then, mvien.9=1, and the supervisor external interrupt signal is 1, so mip.SEIP is still 1 Then, a write to mvip.SEIP=0 Then, the supervisor external interrupt signal is 0, so mip.SEIP becomes 0 Then, a write to mvien.9=0 Should mip.SEIP be 0 here or 1?