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riscv / riscv-aia

https://jira.riscv.org/browse/RVG-59
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MSI page tables apply to all forms of memory accesses #28

Closed jhauser-us closed 2 years ago

jhauser-us commented 2 years ago

... Not just naturally aligned 32-bit writes.

Signed-off-by: John Hauser 31252952+jhauser-us@users.noreply.github.com

jhauser-us commented 2 years ago

Requiring an IOMMU to return 0 as the read value imposes a significant burden on the IOMMU construction to have a read data return path to the I/O bridge and for the I/O bridge to have a completion buffer to hold data that can be filled by either the IOMMU returned data or data returned from the memory subsystem.

I'm willing to change the text to say that the IOMMU should preferably return zero (first choice), else it should abort the read (second choice).

But I think you're being insufficiently creative in thinking about possible implementations. The response message that returns zero for the read doesn't have to be generated by the IOMMU itself, or even by the I/O bridge. The IOMMU could signal back to the I/O bridge that zero should be returned---which takes at most one extra wire between the two components---and the I/O bridge might respond to that by, for example, redirecting the original read request to a known page of read-only zeros in the machine's address space, if that's the easiest way to handle it. Given that the transaction is known to be a read, the physical address of any IMSIC interrupt file will do.

ved-rivos commented 2 years ago

Thanks. Having those two options suffices.