Add clarification about MSI write replaced by MRIF update

[ved-rivos]

Would also be good to add the following clarifications: The memory write to set the pending bit in MRIF must follow the ordering rules as applicable to the original MSI write from the device. For PCIe, for example, this implies that a) the memory write to set the pending bit must not be visible to any agent before all previous posted requests from that device are visible to all agents and b) later read completion from that device must not be delivered before the write to set the pending bit in MRIF is visible to all agents.

[jhauser-us]

@ved-rivos, I disagree. Topics beyond the scope of the AIA include details of ordering rules for transactions over PCIe or any other specific buses, and most details about synchronizing software to IOMMU-relevant events, which I understand is part of you folks' original motivation for these clarifications. If you believe you need these additional requirements, you can put them in the RISC-V IOMMU spec. They are too IOMMU-specific and bus-specific for the AIA.