riscv / riscv-aia

https://jira.riscv.org/browse/RVG-59
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Possible typos in table 6.1 #63

Closed jrahmeh closed 9 months ago

jrahmeh commented 9 months ago

Given that bit 10, 6, and 2 in hideleg correspond to bits 9, 5, and 1 in the vsip/vsie CSRs, it seems that some of the bit indices in table 6.1 is off by 1. Instead of vsip[n], we should have vsip[n-1]: this way when hiedelg[10] is zero, vsip[9] is read only zero.

Similarly, sip[n], vsie[n], and sie[n] should all be indexed with n-1.

jhauser-us commented 9 months ago

The caption for Table 6.1 says:

The effects of hideleg and hvien on vsip and vsie for major interrupts 13-63.

None of the bit numbers you mentioned (10, 6, 2, or 9, 5, 1) are for major interrupts in the range 13-63.

jrahmeh commented 9 months ago

Thanks for the clarification