The interrupt-pending and interrupt-enable bits are stored interleaved by doublewords within an MRIF to facilitate the possibility of an IOMMU examining the relevant enable bit to determine whether to send a notice MSI after updating a pending bit, rather than the default behavior of always sending a notice MSI after an update without regard for the interrupt-enable bits. The memory arrangement matters only when MRIFs are supported without atomic update.
I don't understand the last sentence. In my understand, if supported without atomic update, IOMMU can't specify the interrupt enable state at the time it update the interrupt pending state. Also, when supported with atomic update, if ip and ie bits of a interrupt are far from each other, IOMMU can't do this too. So in my undersatand, the interleaving of ie and ip array is only matter for IOMMU with atomic support, while it is always impossible for IOMMU without atomic support to examine the relevant enable bit to determine whether to send a notice MSI after updating a pending bit.
On page 86:
I don't understand the last sentence. In my understand, if supported without atomic update, IOMMU can't specify the interrupt enable state at the time it update the interrupt pending state. Also, when supported with atomic update, if ip and ie bits of a interrupt are far from each other, IOMMU can't do this too. So in my undersatand, the interleaving of ie and ip array is only matter for IOMMU with atomic support, while it is always impossible for IOMMU without atomic support to examine the relevant enable bit to determine whether to send a notice MSI after updating a pending bit.