search

riscv / riscv-aia

https://jira.riscv.org/browse/RVG-59
Creative Commons Attribution 4.0 International
81 stars 19 forks source link

mvien[1] #77

Open Mei-x-l opened 7 months ago

Mei-x-l commented 7 months ago

1.mvien[1] =0 , external interrupt controller give a intrrupt setting mip.ssip = 1 2.should mvip.ssip[1] change from 0 to 1 ?

jhauser-us commented 6 months ago

The AIA document in Section 5.3, "Interrupt filtering and virtual interrupts for supervisor level", says,

When bit 1 of mvien is zero, bit 1 of mvip is an alias of the same bit (SSIP) of mip.

So when mvien[1] = 0, mip.SSIP and mvip.SSIP are two views of the same bit. If mip.SSIP changes, mvip.SSIP obviously also changes, as they are actually the same bit.