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riscv / riscv-aia

https://jira.riscv.org/browse/RVG-59
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Conflict register model between MVIEN and HVIEN #78

Open zetalog opened 7 months ago

zetalog commented 7 months ago

Original thread here: https://github.com/riscv/riscv-aia/issues/64

The issue can be reconsidered using register model point of view.

IMO, when understanding MVIEN, one should refer to HVIEN spec words as a cross reference. IMO, MVIEN is added by AIA just because nested virtualization requires MVIEN to S-mode to act as equivalent as HVIEN to HS-mode. Thus, yes, spec is wrong for MVIEN, but it is wrong not because it controls MVIP (it shouldn't control MVIP), but it should be designed equivalent to HVIEN which controls multiple invisible SIP bits for virtual machines. So we should fix the SPEC along the other way.

SPEC actually dictates this clearly in a different paragraph. MVIP/HVIP which is still a single M-mode/HS-mode bit (whatever it is an aliasing bit or logically ORed bit), is a kind of usage model, known as interrupt filtering. This usage model is designed for traditional RISC-V machines where CLINT MTIP is meant to be filtered as STIP and this bit is made visible in AIA as MVIP. However, MVIEN/HVIEN is implemented as a totally different usage model, controlling multiple S-mode/VS-mode bits, which is known as virtual interrupt.

AIA introduces the new virtual interrupt usage model, just because the original interrupt filtering model (virtualized in the lower privileged mode) is not such useful for virtual machines and extended major interrupts (should have virtualized bits in the upper privileged mode).

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As a conclusion, I don't think MVIEN controls an alias of MVIP, but should control an alias of SIP virtual interrupt bit and this bit is invisible to MIP and MVIP.

So why don't we just leave SEIP original usage model to MVIP and don't let it bother the new register model since software won't suffer from the original usage model when they are going to use the new register model?

zhuotianshu commented 6 months ago

Sorry, I can't understand these two paragraph:

MVIP/HVIP which is still a single M-mode/HS-mode bit (whatever it is an aliasing bit or logically ORed bit), is a kind of usage model, known as interrupt filtering. This usage model is designed for traditional RISC-V machines where CLINT MTIP is meant to be filtered as STIP and this bit is made visible in AIA as MVIP. However, MVIEN/HVIEN is implemented as a totally different usage model, controlling multiple S-mode/VS-mode bits, which is known as virtual interrupt.

In my view, interrupt filtering and virtual interrupts share the same concept. Enforcing filtering is not possible if S mode interrupts can still be automatically triggered by M mode interrupts. Therefore, it is necessary to use a switch to disable M mode interrupts from triggering S mode interrupts when you wish to activate the filtering. MVIEN acts as that switch. And only after that, you can use MVIP to inject virtual interrupts without the disturb from M mode interrupts.