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riscv / riscv-aia

https://jira.riscv.org/browse/RVG-59
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Optional setting of interrupt pending when writing sourcecfg? #80

Closed kdockser closed 3 months ago

kdockser commented 4 months ago

The spec states:

Any write to a sourcecfg register might (or might not) cause the corresponding interrupt-pending bit to be set to one if the rectified input value is high (= 1) under the new source mode.

Is this intended to mean that there is no architectural requirement for an interrupt pending bit to be set in such a case. Or is intended to mean that there are other factors that impact the architectural behavior in such a case?

More specifically, in MSI mode when switching from Detached to Level Zero and the incoming wire value is zero, is it required that the corresponding interrupt-pending bit to be set to one? It seems like the answer is no since the inversion of the incoming wire value is a constant 1.

jhauser-us commented 3 months ago

More specifically, in MSI mode when switching from Detached to Level Zero and the incoming wire value is zero, is it required that the corresponding interrupt-pending bit to be set to one? It seems like the answer is no since the inversion of the incoming wire value is a constant 1.

You are correct; the answer is "No". In the situation you describe, if the interrupt-pending bit was zero before the write to sourcecfg, it might get set to one, or it might remain zero. Either outcome is allowed.