jhauser-us
commented
2 weeks ago The same Section 3.6 you quoted goes on to say:
If a machine’s construction dictates that harts be subdivided into groups, with each group relegated to its own portion of the address space, then the best that can be achieved is to locate together the machine-level interrupt files of each group of harts separately, and likewise locate together the supervisor-level and guest interrupt files of each group of harts separately. This situation is further addressed later below.
And then in commentary:
A system may divide harts into groups in the address space because each group exists on a separate chip (or chiplet in a multi-chip module), and weaving together the address spaces of the multiple chips is impractical.
Hence, if you need to separate the addresses for the IMSICs located on different dies (chips), then you can put each die's IMSICs in a separate "group". The formulas you refer to in Section 4.9.1 also explicitly account for these groups, which you didn't mention.
On the other hand, it will reduce the need for PMP entries if you can manage to have all IMSICs in a single group, all together in the address space (separately for M and S levels). Fewer of these groups is better for PMP use.
Assume that a multi-socket SoC is packaged with multiple dies in each socket, and each die integrates IMSIC. How should the addresses of the interrupt files of the IMSICs be arranged?
From AIA spec 3.6, “When practical, the memory pages of the machine-level interrupt files of all IMSICs should be located together in one part of the address space, and the memory pages of all supervisor-level and guest interrupt files should similarly be located together in another part of the address space, according to the rules below”
The Chapter 4.9.1 shows the formula of MSI address calculation, the mmsiaddrcfg, mmsiaddrcfgh, smsiaddrcfg, and smsiaddrcfgh should be programmed once, and the target register can be programmed for each interrupt source. According to my understanding, after the msiaddrcfg configuration determines the base PPN, the calculation of the MSI address can only be mapped to an interrupt file within one die, and it seems impossible to configure different sources to different dies or sockets. If the interrupt files of each die are arranged according to the addresses of each die, instead of being uniformly arranged for all interrupts.
So, if we need to program 1023 interrupt source to different die or different socket, we must put all the interrupt files together in physical address space, right?