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riscv / riscv-aia

https://jira.riscv.org/browse/RVG-59
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AIA: contradiction in bits 12:0 of hvip description #93

Closed evgeniy-paltsev closed 3 weeks ago

evgeniy-paltsev commented 2 months ago

The current AIA documentation has a contradiction in a part describing bits 12:0 of hvip:

Bits 12:0 of hvip are reserved and must be read-only zeros, while bits 12:0 of hvip are defined by the RISC-V Privileged Architecture. Specifically, bits 10, 6, and 2 of hvip are writable bits...

From chapter 6.3.2. Virtual interrupts for VS level

We specify (without any condition) that 12:0 bits of hvip are read-only zeros and writable at a same time. It seems to be a typo and the first part of phrase could be about hvien instead of hvip. So, proper phrasing could be:

Bits 12:0 of hvien are reserved and must be read-only zeros

Could you please confirm if it is just a typo or I misunderstand the phrasing in the docs?

jhauser-us commented 1 month ago

The document you are looking at is the one generated from the AsciiDoc sources, which still contain many errors. In my opinion, it should never have been released as the "correct" version, because it's often not correct. I just deleted that ill-advised release.

Please discard the file you have. You can obtain the specification that was actually ratified here: https://github.com/riscv/riscv-aia/releases/tag/1.0

Eventually, the AsciiDoc version will be made to match the ratified specification, but it's not there yet.

evgeniy-paltsev commented 3 weeks ago

Marking as closed as the problematic release was removed.