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riscv / riscv-aia

https://jira.riscv.org/browse/RVG-59
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Can hvictl inject an interrupt with IID=0 and IPRIO=0? #98

Open zhuotianshu opened 1 month ago

zhuotianshu commented 1 month ago

Spec explicitly states that such an interrupt cannot be generated in M mode:

To ensure that mtopi is never zero when an interrupt is pending and enabled for machine level, if major interrupt 0 can trap to M-mode, it must have a default priority lower than a machine external interrupt.

And so does S mode. But there seems no similar statement around the description of vstopi. So what will happen if hvictl has VTI=1, IID=0 and IPRIO=0?

jhauser-us commented 1 month ago

I assume you meant also to add the conditions that hvictl has DPR = 0 and IPRIOM = 1. In that case, the answer to the title's question is, you can try to inject that interrupt, but it won't work.

With all fields of hvictl being zeros except VTI = 1 and IPRIOM = 1, it is possible for the interrupt represented by hvictl to be the highest-priority candidate for vstopi, which will leave vstopi with IID = 0 and IPRIO = 0. But then no interrupt will actually be taken, because vstopi is all zeros.

If any other lower-priority interrupts are pending-and-enabled, this value of hvictl will actually block them from being taken.

Note that if hvictl.IPRIOM = 0, the value of vstopi.IPRIO will be 1. And if hvictl has IPRIOM = 1 and DPR = 1 (and if there is no pending-and-enabled external interrupt), then vstopi.IPRIO will be 255. Those settings will allow an interrupt with IID = 0 to occur.