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riscv / riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension
https://jira.riscv.org/browse/RVG-122
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clmul: fix loop-end condition in the sail code #158

Closed hirooih closed 1 year ago

hirooih commented 3 years ago

Although the last iteration does not affect on the output, it is redundant.

xlen:32

  + 32: 31 30 29 ... 02 01 00
+ | 31:    31 30 29 ... 02 01 00
| |                 .
| |                 XOR
| |                 .
| + 01:                    31 30 29 ... 02 01 00
+   00:                       31 30 29 ... 02 01 00
        |<---  clmulh   --->| |<---   clmul   --->|
           |<---  clmulr   --->|

clmul:  0 to (xlen – 1)
clmulh: 1 to  xlen
clmulr: 0 to (xlen – 1)