remove the M-bit from AP

riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

https://jira.riscv.org/browse/RVG-148

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remove the M-bit from AP #268

Closed tariqkurd-repo closed 4 months ago

tariqkurd-repo commented 4 months ago

The M-bit is no longer in the AP field as it's not a permission

tariqkurd-repo commented 4 months ago

Fixes https://github.com/riscv/riscv-cheri/issues/260