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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
Creative Commons Attribution 4.0 International
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change utidc address to avoid conflict #275

Closed tariqkurd-repo closed 1 month ago

tariqkurd-repo commented 1 month ago

Fixes https://github.com/tariqkurd-repo/riscv-cheri/pull/new/utid_address

PRugg-Cap commented 1 month ago

Shouldn't it have upper 2 bits 0b11 to make it read-only?

tariqkurd-repo commented 1 month ago

of course, I forgot that it was supposed to be read only - I'll reallocate

PRugg-Cap commented 1 month ago

Thanks!