This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
there's no spec change here, but it clarifies the relationship between C.FSDSP, Zcmp, Zcmt and Zilsd, and for RV32 and RV64
plus some tidy up of instruction pages I spotted on the way
an important point is that Zcmp/Zcmt cannot exist in RV64 cap mode, as the same encodings are mapped to C.FSDSP. This shouldn't be a problem as the Zcm extensions are only really intended for RV32.
this started out as a note about Zilsd but expanded rather to correctly address https://github.com/riscv/riscv-cheri/issues/274
there's no spec change here, but it clarifies the relationship between C.FSDSP, Zcmp, Zcmt and Zilsd, and for RV32 and RV64
plus some tidy up of instruction pages I spotted on the way
an important point is that Zcmp/Zcmt cannot exist in RV64 cap mode, as the same encodings are mapped to C.FSDSP. This shouldn't be a problem as the Zcm extensions are only really intended for RV32.