This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
clarify the mapping of 16-bit encodings like C.FLW and C.FLD in int mode and cap mode for RV32 and RV64
it's confusing, so these tables help me understand what's going on
clarify the mapping of 16-bit encodings like C.FLW and C.FLD in int mode and cap mode for RV32 and RV64 it's confusing, so these tables help me understand what's going on
no spec change - just clarification