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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Fix capability address align exception priority #288

Closed PRugg-Cap closed 3 months ago

PRugg-Cap commented 3 months ago

Fixes https://github.com/riscv/riscv-cheri/issues/286