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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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acperm: clarify ASR rule for MXLEN=32 #289

Closed martin-kaiser closed 2 weeks ago

martin-kaiser commented 2 weeks ago

Fix a contradiction between acperm rule 1 for MXLEN=32 and table 3.

Table 3 shows that for MXLEN=32, the ASR bit can be set only if all of R, W, C and X are set. Rephrase rule 1 to be in line with this.