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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Replace references to T8 with L8 in the bounds encoding, and provide … #291

Closed buxtonpaul closed 2 weeks ago

buxtonpaul commented 2 weeks ago

The field T8 is named incorrectly and should be L8 to indicate the field contains bit 8 of the length. Which is used to compute then top field for the capability.

Resolves issue #(290) https://github.com/riscv/riscv-cheri/issues/290

buxtonpaul commented 2 weeks ago

I have re-pushed to the branch fixing both the length typo as well as any line ending issues(I hope)

tariqkurd-repo commented 2 weeks ago

I have re-pushed to the branch fixing both the length typo as well as any line ending issues(I hope)

I don't see another commit?!

buxtonpaul commented 2 weeks ago

It was an amend commit which replaced the original

andresag01 commented 2 weeks ago

@PeterRugg : Would you like to take a look at these changes?

PRugg-Cap commented 2 weeks ago

Yep, looks like the right fix