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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
Creative Commons Attribution 4.0 International
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Minor rephrasing for L8 bit description #292

Closed gameboo closed 2 weeks ago

gameboo commented 2 weeks ago

L8 is not directly a top address bit, so this avoids confusion