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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Representability check description doesn't capture address-wrapping edge cases #293

Open PRugg-Cap opened 2 weeks ago

PRugg-Cap commented 2 weeks ago

The description of the representability check is slightly imprecise in cases where the base or top want to wrap the address space. A correction is described in the bounds section: https://github.com/riscv/riscv-cheri/blob/8f587528c7d1a0005be68c38d955408bb22485f2/src/cap-description.adoc?plain=1#L501-L502

but not in the representable region section, where it is also relevant: https://github.com/riscv/riscv-cheri/blob/8f587528c7d1a0005be68c38d955408bb22485f2/src/cap-description.adoc?plain=1#L649-L653

In addition, we need to clarify what happens if the base wraps.

I'll need to think about how to describe this precisely, but just wanted to record the issue so it doesn't get missed. I don't think there's a bug, but somebody trying to implement it just from this description would certainly get confused!

tariqkurd-repo commented 1 week ago

PR for this one? @PRugg-Cap ?

PRugg-Cap commented 1 week ago

Not yet, sorry, I'll try tomorrow!