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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Compressed address CSRs DDC and DDDC should not be referred to as exectuable vectors #297

Closed jamie-melling closed 5 days ago

jamie-melling commented 1 week ago

Current spec

Some CSRs store executable vectors as shown in Table 43.

Should be along the lines of:

Some CSRs store executable vectors or are data pointers shown in Table 43.

tariqkurd-repo commented 1 week ago

https://github.com/riscv/riscv-cheri/pull/299

andresag01 commented 5 days ago

299 is already merged, so this ticket can now be closed.