This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
The description of C.JALR links to JALR. In the JALR the PCC's offset is incremented by 4 and then written to the cd register. However, I think for C.JALR, it seems necessary to increment the PCC by 2 because the instruction is only 16 bits long.
The description of
C.JALRlinks toJALR. In theJALRthe PCC's offset is incremented by 4 and then written to thecdregister. However, I think forC.JALR, it seems necessary to increment the PCC by 2 because the instruction is only 16 bits long.