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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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swap sense of M-bit, so that 0 is cap mode #305

Closed tariqkurd-repo closed 5 days ago

tariqkurd-repo commented 6 days ago

it makes more sense for zero to mean cap mode, as it's the same as not having hybrid mode

tariqkurd-repo commented 6 days ago

fixes https://github.com/riscv/riscv-cheri/issues/303