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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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T8, TE & TB Clarifications #306

Open tony-cole opened 6 days ago

tony-cole commented 6 days ago

Re: riscv-cheri-v0.8.2.pdf

Section: 2.2.6. Bounds (EF, T, TE, B, BE)

T8 is confusing, maybe call it T8_E4? As it’s T8 when EF=1 or E4 when EF=0.

Initially I thought TE and BE were the Exponents for the Top and Bottom bounds respectively, is it not made clear (in this section) that they are actually combined as { TE, BE } to produce the exponent for both the top and bottom bounds (when EF=0). Also, it’s not made clear that they are the LS-bits of T & B when EF=1.

It is not made clear (in this section) that the top 2-bits of T are recreated on decode and so have be omitted in the encoding.

andresag01 commented 4 days ago

Please note that the T8 bit was renamed to L8 (https://github.com/riscv/riscv-cheri/pull/291) because it is related to the length, not the top address.