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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Decoding pseudo-code clarification/fix #309

Open tony-cole opened 6 days ago

tony-cole commented 6 days ago

Re: riscv-cheri-v0.8.2.pdf the Decoding pseudo-code on page 14.

For the calculations of ct and cb to be correct, R needs to be bounded to MW bits, as follows: R[MW-1:0] = B - 2^MW-2^

and note that the comparisons in Tables 8 & 9 are unsigned.

andresag01 commented 5 days ago

@tony-cole : This part of the spec is only a place-holder and the current notation is not terribly well-defined as you point out. This is because the text is temporary and will eventually be replaced with auto-generated fragments of SAIL extracted from the open-source RISC-V CHERI SAIL model.

We should keep it like this for now and revisit when the SAIL is available. Note that we've had similar comments in the past.