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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Prefetch instruction sections does not mention the various malformed checks #312

Closed jamie-melling closed 5 hours ago

jamie-melling commented 4 days ago

It was missed when doing https://github.com/riscv/riscv-cheri/pull/285

tariqkurd-repo commented 4 days ago

ok - so the prefetch should be dropped if the reserved bits are set, the permissions are bad or the bounds are malformed, i.e. if there's anything wrong so the cap can't be used.