This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
In section 5.7 Disabling CHERI Registers the description points to Sections 3.3 and 8.5 for instructions that should generate exceptions. Whilst the text does say CHERI instructions, it is quite easy to read it as all instructions in table 8.5 would generate an exception.
Suggest either
Add column to the table in 8.5 to indicate clearly the instructions specified.
Reword the sentence to make it clear that not all the instructions in 8.5 are CHERI instructions. E.g.
The instructions in Section 3.3 and the CHERI instructions in Section 8.5 cause illegal instruction exceptions.
In section 5.7 Disabling CHERI Registers the description points to Sections 3.3 and 8.5 for instructions that should generate exceptions. Whilst the text does say CHERI instructions, it is quite easy to read it as all instructions in table 8.5 would generate an exception. Suggest either