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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Integer pointer mode in debug mode #322

Open andresag01 opened 1 month ago

andresag01 commented 1 month ago

The current CHERI RISC-V spec goes to great length to provide a "compatibility" mode with CHERI-less RISC-V when executing code in M, S and U mode provided that Zcherihybrid is implemented. However, the machine always enters debug in capability pointer mode. Should there be an option to enter debug mode in "integer pointer mode", perhaps something like a CRE?

NOTE: I am only pointing out that a CHERI machine supporting Zcherihybrid would need a CHERI-aware debugger even though, for whatever reason, it is only ever running non-CHERI aware code compiled by a non-CHERI aware compiler.

andresag01 commented 1 month ago

@tariqkurd-repo @jrtc27 : Do you have a view on this?

tariqkurd-repo commented 1 month ago

The debugger only needs to issue an SCMODE before running existing debug code, but it's a reasonable point that something does have to change. I think it's normal to have to customise debugger software for specific cores anyway, just look at how many debug options there are in the RISC-V spec. Also I think that a CHERI core is likely to be delivered with a customed debugger, which in this case will include the update to switch modes, or more likely to have full CHERI support available in the debugger.

Your proposal is simple enough - but I'd hold off until the need for it is demonstrated.

I'm pretty sure that @jrtc27 will have an opinion.