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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Add GCMODE instruction #350

Closed andresag01 closed 1 month ago

andresag01 commented 1 month ago

Add GCMODE instruction that decodes the mode from an arbitrary capability in an x register and writes the value to another x register.

GCMODE allows inspecting a capability's CHERI execution mode without the need for software to "manually" decode the capability's metadata using gchi.

Fixes #302.