Miscellaneous fixes - Githubissues

riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

https://jira.riscv.org/browse/RVG-148

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Miscellaneous fixes #371

Closed andresag01 closed 2 months ago

andresag01 commented 2 months ago

Change introduction sentence to mention capability types instead of sealing
Reduce font in some figures to ensure bit field names do not overflow diagram
Remove "pending extension" section with only CLIC since that is still in development and is generally orthogonal to CHERI

Partially fixes https://github.com/riscv/riscv-cheri/issues/363