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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Compatibility with Zilsd #372

Closed arichardson closed 1 month ago

arichardson commented 1 month ago

It looks like Zilsd (https://github.com/riscv/riscv-zilsd/blob/v0.10/zilsd.adoc) wants to repurpose the DWORD load/store opcodes for RV32 to be load-store pair. Should we use the RV64 encoding of loads/stores for RV32 to avoid this conflict?

This would solve the non-compressed conflict, however for compressed instructions they are are using the floating-point load-stores and forcing capability loads to use the RV64 format would prevent push-pop instructions from being supported. Not sure how best to approach this problem.

arichardson commented 1 month ago

https://lists.riscv.org/g/tech-arch-review/message/259 suggests this extension looks likely to be ratified as-is?

tariqkurd-repo commented 1 month ago

The confusing 16-bit encoding mapping is why I put this table in the doc:

image

So - I would say - that no change is needed for compressed encodings - as we already support both Zcmp (push/pop) and Zcmt (table jump) in cap mode.

For the 32-bit encodings - then we have quite a few which change depending on XLEN - so I think I'd be in favour of unifying all of them. Apart from anything else it will simplify the document - so my proposal is to move all load/store/AMO cap encodings to the RV64 ones.

arichardson commented 1 month ago

Simplifying the encodings to be consistent across XLEN for 32-bit encodings sounds good to me!