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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Indicate GCMODE output for non-X caps #377

Closed andresag01 closed 2 months ago

andresag01 commented 2 months ago

Change the specification for GCMODE so that it returns 0 when the input capability goes not have the X permission set.

Fixes https://github.com/riscv/riscv-cheri/issues/376

tariqkurd-repo commented 2 months ago

this doesn't include reserved bits being non-zero, or GCTYPE which has the same problem

andresag01 commented 2 months ago

this doesn't include reserved bits being non-zero, or GCTYPE which has the same problem

It is generally not a policy for these getter instruction's output to be dependent on whether the input capability is corrupted or not. It would be best to keep this idea, otherwise we will need to change other instructions like GCLEN, GCTYPE, GCPERM, ACPERM, etc to conform