search

riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
Creative Commons Attribution 4.0 International
57 stars 30 forks source link

Corner cases for SCMODE #384

Closed andresag01 closed 2 months ago

andresag01 commented 2 months ago

SCMODE currently does not change the capability if mode cannot be set because the permissions are invalid or x is not granted. Should this behavior change to, for example, clear the tag of the capability?

This ticket was created after feedback in https://github.com/riscv/riscv-cheri/pull/382

tariqkurd-repo commented 2 months ago

unless there's a very compelling reason to change it I suggest to stabilise the spec as it is

andresag01 commented 2 months ago

@tariqkurd-repo : Agreed. I do not have a compelling reason, so I will close this ticket. Please feel free to re-open if this changes.