riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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remove false comments from RV32 permission encoding table #386

Closed tariqkurd-repo closed 2 months ago

tariqkurd-repo commented 2 months ago

quadrants 2 and 3 has a false comment copy/pasted from quadrant 0 most likely