riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Align authors and contributor lists #388

Closed andresag01 closed 2 months ago

andresag01 commented 2 months ago

Add missing names in the author list that were in the contributors lists (https://github.com/riscv/riscv-cheri/blob/main/src/contributors.adoc)