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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Make FP reg operand notation consistent #398

Closed andresag01 closed 2 months ago

andresag01 commented 2 months ago

Fixes #395 using the same notation from the RISC-V unprivileged ISA spec

tariqkurd-repo commented 2 months ago

you've changed the assembly syntax which does use the f notation it is a bugbear of mine that risc-v use integer src/dsts for fpu instructions, it makes their spec much harder to use but certainly the encoding should use rd, rs1, rs2 to be consistent