This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
All possible entries in quadrant 1 grant execute permission. Tick the X column in table 28 for all quadrant 1entries. This is consistent with the Notes and with table 4.
All possible entries in quadrant 1 grant execute permission. Tick the X column in table 28 for all quadrant 1entries. This is consistent with the Notes and with table 4.