clarify that quad 2 and 3 entries 4 and 5 are reserved when LVLBITS=2

riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

https://jira.riscv.org/browse/RVG-148

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clarify that quad 2 and 3 entries 4 and 5 are reserved when LVLBITS=2 #442

Closed tariqkurd-repo closed 3 weeks ago

tariqkurd-repo commented 3 weeks ago

also note that Zcherilevels with LVLBITS=1 is in the prototype phase, I think LVLBITS=2 will need more analysis to prove that the spec is correct (at least for the ACPERM rules).