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riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
Creative Commons Attribution 4.0 International
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reinstate mstatus.CRG with justification #445

Closed tariqkurd-repo closed 2 weeks ago

tariqkurd-repo commented 2 weeks ago

mstatus.CRG is back so as not to break the SAIL model