This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
The current definition of the ZCheripte bits will cause any software that doesn't know about the pte.crg and pte.cw bits to be incapable of running with PTE support enabled.
OS's which do not know/care about zcheripte running on a cheri processor will be unable to use capabilities as they will never set the pte.cw or pte.crg bits meaning that capabilities can never be stored to or loaded from memory.
We will require either a mode of operation which defaults to no zcheripte and can be explicitly enabled. Or require that all cheri implementations wanting to use virtual memory must also use zcheripte.
The current definition of the ZCheripte bits will cause any software that doesn't know about the pte.crg and pte.cw bits to be incapable of running with PTE support enabled. OS's which do not know/care about zcheripte running on a cheri processor will be unable to use capabilities as they will never set the pte.cw or pte.crg bits meaning that capabilities can never be stored to or loaded from memory.
We will require either a mode of operation which defaults to no zcheripte and can be explicitly enabled. Or require that all cheri implementations wanting to use virtual memory must also use zcheripte.