riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
Creative Commons Attribution 4.0 International
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Switch all wavedrom diagrams to output svg images. #10

Closed rajnesh-kanwal closed 6 months ago

rajnesh-kanwal commented 6 months ago

This is a workaround to fix https://github.com/riscv/riscv-isa-manual/issues/1019 issue. For some reason wavedrom doesn't output CSR field names or any other diagram text in png format but works fine for svg format.

rajnesh-kanwal commented 6 months ago

@bcstrongx

bcstrongx commented 6 months ago

thanks!