This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
This is a workaround to fix https://github.com/riscv/riscv-isa-manual/issues/1019 issue. For some reason wavedrom doesn't output CSR field names or any other diagram text in png format but works fine for svg format.
This is a workaround to fix https://github.com/riscv/riscv-isa-manual/issues/1019 issue. For some reason wavedrom doesn't output CSR field names or any other diagram text in png format but works fine for svg format.