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riscv-control-transfer-records
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
Creative Commons Attribution 4.0 International
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11 john hauser feedback 1
#12
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bcstrongx
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5 months ago