search

riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
Creative Commons Attribution 4.0 International
14 stars 4 forks source link

Wrong bits referred to in sctrctl #15

Closed jhauser-us closed 4 months ago

jhauser-us commented 4 months ago

Section 2.2 says:

Bits 0 and 8 in sctrctl are read-only 0.

Since those fields moved, I believe it should now be bits 2 and 9.

rajnesh-kanwal commented 4 months ago

Added fix in https://github.com/riscv/riscv-control-transfer-records/pull/23. @bcstrongx can you please review and merge this? Thanks.

bcstrongx commented 4 months ago

Somehow I didn't see this. But yes, I'll make the fix, thanks.

bcstrongx commented 4 months ago

Resolved by https://github.com/riscv/riscv-control-transfer-records/pull/23