sctrstatus.FROZEN isn't WARL

riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

https://jira.riscv.org/browse/RVG-62

Creative Commons Attribution 4.0 International

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sctrstatus.FROZEN isn't WARL #17

Closed jhauser-us closed 3 months ago

jhauser-us commented 4 months ago

The spec appears to require that bit FROZEN is always implemented as writable in sctrstatus, supporting both values 0 and 1, so how can it be WARL?