riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
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"RAS Emulation Mode" should be "RAS Mode"? #18

Closed jhauser-us closed 4 months ago

jhauser-us commented 7 months ago

Does RAS Emulation Mode actually emulate anything? Wouldn't this be better called simply "RAS Mode"?

bcstrongx commented 6 months ago

I'd argue that, when RASEMU=1, the CTR buffer is emulating a return-address stack (RAS). Returns do not actually use the addresses pushed onto it, so it is not an actual RAS.

bcstrongx commented 6 months ago

Let me know if you disagree John, otherwise I'll close the issue at the end of this week.