This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
SCTRCLR raises ... a virtual-instruction exception in VU-mode.
This is misleading when mstateen0.CTR = 0, because attempting to execute SCTRCLR in that case must raise an illegal-instruction exception even in VU-mode.
I think a sufficient fix would be simply for Section 4.1 to explicitly defer to Chapter 5 as is done elsewhere in the spec.
Section 4.1, "Supervisor CTR Clear Instruction", says:
This is misleading when
mstateen0.CTR = 0, because attempting to execute SCTRCLR in that case must raise an illegal-instruction exception even in VU-mode.I think a sufficient fix would be simply for Section 4.1 to explicitly defer to Chapter 5 as is done elsewhere in the spec.