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riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
Creative Commons Attribution 4.0 International
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Drop superfluous condition on S-mode being implemented #20

Closed jhauser-us closed 6 months ago

jhauser-us commented 7 months ago

Section 6.1.2, "External Traps", says:

sctrctl.STE must be implemented if S-mode is implemented

But S-mode is now required, so the condition is superfluous.

bcstrongx commented 6 months ago

Resolved by https://github.com/riscv/riscv-control-transfer-records/commit/120b421d39d8ddf022e9684e77fdf805dbcc21e5