This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
If the H extension is implemented and mstateen0.CTR=1, the hstateen0.CTR bit controls access to supervisor CTR state when V=1. This state includes ... sctrdepth ....
Actually, an attempt to access sctrdepth when virtualization mode V = 1 always raises an exception, either an illegal-instruction exception if mstateen0.CTR = 0 or a virtual-instruction exception if mstateen0.CTR = 1. The value of hstateen0.CTR is irrelevant to this case.
Chapter 5, "State Enable Access Control", says:
Actually, an attempt to access
sctrdepthwhen virtualization mode V = 1 always raises an exception, either an illegal-instruction exception ifmstateen0.CTR = 0 or a virtual-instruction exception ifmstateen0.CTR = 1. The value ofhstateen0.CTR is irrelevant to this case.