Attempts to access sctrdepth from VU-mode act the same as VS-mode

riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

https://jira.riscv.org/browse/RVG-62

Creative Commons Attribution 4.0 International

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Attempts to access sctrdepth from VU-mode act the same as VS-mode #22

Closed jhauser-us closed 3 months ago

jhauser-us commented 4 months ago

Section 2.4 on CSR sctrdepth says:

Attempts to access sctrdepth from VS-mode raise a virtual-instruction exception, ....

This applies to VU-mode too.